The principle of operation of NAND-memory

Modern mobile gadgets, increasing the speed of computer systems and the production of inexpensive but fast drives for storing large amounts of information are directly related to memory chips.

High-speed storage devices use flash memory chips. They were announced in 1988-89, when Intel and Toshiba introduced NOR (Intel) and NAND (Toshiba) memory architectures. It was the second variety that became the most popular, as it had more opportunities for miniaturization. Why, now we’ll figure it out.

Floating gate field effect transistor – the basis of the memory cell
The basis of all flash memory technology, including NAND, is a floating gate field-effect transistor. In general, its structure looks like this:

Before us is an ordinary field-effect transistor, which, in addition to the control one, has another gate. So in this shutter, called “floating”, just lies the whole feature of the technology.

The fact is that this gate and the semiconductor, which is the transistor channel between the drain and the source, are separated by a thin layer of dielectric. Electrons subjected to a positive voltage to the gate will not only be able to follow their usual path inside the semiconductor, but also “jump” by injection or tunneling through the dielectric layer into the floating gate.

Of course, not all electrons can do this, but only a part of them – those that have received more energy. At the same time, they do not penetrate the dielectric layer in the physical sense, but, in accordance with their quantum wave properties, “jump” immediately into the floating gate. The “jumped” electrons cannot return back, since they do not have enough energy for this.

That is, we can apply voltage and thereby “drag” the electrons into the floating gate. They will remain there the next time we turn on the transistor – the charge concentrated on the floating gate will affect the channel located below them between the drain and the source: it will pass or not pass current through the transistor, regardless of the voltage on the control gate. In the simplest case, we get two states – there is current or there is no current. Zero and one. Which is what we needed.

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Moreover, this state can persist for a long time. Of course, this time is not infinite. Gradually, the charge on the “floating” gate will be lost. But this time is quite enough to store information in real conditions of use, since we are talking about years.

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Of course, the recorded information, that is, the charge on the floating gate, can be erased. To do this, it is enough to apply a voltage of reverse polarity to the control gate so that the electrons can leave the floating gate and return to the conductive channel of the transistor. Until this time, the charge and the logical state of the transistor are preserved due to the fact that the energy of the electrons is not enough to overcome the potential and physical barrier in the form of a thin dielectric layer.

In the process of development and miniaturization, the manufacturing technology of floating gate field-effect transistors has changed and improved. If the first memory elements were created in a planar form on the surface of a crystal, now 3D NAND or V-NAND technology (different marketing names) is used, in which the transistor structure is formed not on a horizontal plane, but on a vertical one. This allows you to save space and increase the amount of memory that is placed in one chip. The principle of operation of the transistor remains the same.

In addition, not only metal floating gates are now used. Chip manufacturing technologies have emerged that increase their reliability and allow them to hold a charge for a longer time. For example, Samsung uses isolated areas of non-conductive silicon nitride SiN to trap charges and act as a “floating gate”. They are called 3D Charge Trap Flash – “charge traps”. Their use increases the storage life of the charge, and, consequently, the information in the cell, and also makes microcircuits more economical in terms of power consumption.

NAND and NOR memory cells – how they work
Floating gate transistors are connected into matrices that store words of data at the desired addresses in various ways. The main ones are NAND and NOR. These abbreviations are abbreviations for the phrases “Not AND” and “Not OR” – respectively “AND-NOT” and “OR-NOT”.

Schematically, the way to construct matrices in two cases looks like this:

As you can see from the presented schemes, building a matrix according to the NOR scheme is convenient because you can simply access any specific cell and write information to it. In the case of NAND, several single memory cells are connected in series, and in order to write the “zero” state to one of them, all the others must be open and pass current.256GB SSD M.2 Drive Intel 545s Series [SSDSCKKW256G8X1]
It is for this reason that erasing information in NAND-memory chips is done block by block, and in order to write new data, information is updated immediately for many cells (they write “page by page”). But on the other hand, such circuitry made it possible to significantly simplify the topology and reduce the size of memory cells on a chip. Therefore, in modern microelectronics, it is NAND memory that is the main one. And when you buy a new SSD, it contains NAND chips.

How can one cell store up to 4 bits of data
The advantages of NAND memory cells are not limited to small sizes. Another interesting and useful point is that they can record not one, but several (up to four) bits of information. Theoretically, more are possible, but so far we can really talk about only four, since serious technical difficulties begin further. However, at the Flash Memory Summit 2019 event, Toshiba representatives already presented the idea of ​​​​writing five bits of data per cell. But so far, the matter has not yet come to practical application.

Let’s figure out how writing several bits of information into one cell works. A floating gate transistor is an element that can be not only in two states – closed and open, but also in intermediate ones. In fact, this is an analog element capable of passing a current of different magnitudes through the drain-source circuit, depending on how much charge is on the gates and what field it creates.512GB 2.5″ SATA Drive GIGABYTE UD Pro [GP-UDPRO512G]
This means that you can “drive” as many electrons into the floating gate (in 3D NAND – into the “charge trap”) as many electrons as you need to pass a certain current through the transistor at a certain threshold voltage. There can be several such threshold voltages, since it is possible to accumulate a charge more or less – as much as it takes to record the necessary information in the cell. Further, by applying voltage to the transistor and controlling the current, one can judge its state, that is, what data it stores.

Hence, there are memory cells in which not one bit of information is stored, but more, up to four. Therefore, all memory is divided into two categories: SLC (short for Single Level Cell – single-level cells) and MLC (Multi Level Cell – multi-level cells).

With SLC cells, everything is simple. These are classical memory elements that store one bit with two states, one of which corresponds to a charged gate, and the second to a discharged one.

MLC cells, in turn, are divided into:
MLC cells. These are memory elements that can store two bits of information. Accordingly, for this, it is necessary to accurately fix the four operating modes of the transistor in order to understand which of the four data combinations is stored – 00, 01, 10, 11.
TLC cells. TLC is short for Triple Level Cell, a three-level cell. They can store three bits of data, and, therefore, it will be necessary to accurately fix already eight modes of operation of the transistor.
QLC cells. QLC is short for Quad Level Cell, a four-level cell. It already contains four bits of data. But at the same time, it is necessary to fix already 16 operating modes of the transistor.
Such an increase in recording density, on the one hand, increases the volume of drives. But on the other hand, reliability is reduced, since high accuracy of state recording and subsequent data reading is required. The time spent on reading and writing data also increases, since it is necessary to understand which of the 4, 8 or 16 modes the transistor is in.

Future Technology Perspectives
In order to further increase the density of data storage in one cell and switch to storing five bits of information, it will be necessary to control 32 operating modes of the transistor. Considering that the power supply of microcircuits is a few volts, it is about observing the accuracy of measuring and setting threshold voltages in hundredths of a volt. And this is only one of the difficulties that need to be solved.

In addition, it is necessary to solve such problems as error correction, reliability, and the number of write / read cycles. The last problem is one of the most critical, since writing and reading data leads to wear and tear of the dielectric layer between the floating gate and the semiconductor channel of the transistor, and, consequently, to failure of the cell. It is this point that determines the uptime of memory. But it’s possible that engineers will soon find a solution to take the next step in increasing recording density. Then there will be even larger solid-state drives at a low price.